Active LOW input S’-R’ Latch

Active LOW input S’-R’ Latch 


NAND Gate based S'- R' Latch

  • In the Active LOW input S’-R’ Latch, the latch changes its state based on inputs that are in the LOW logic state.
                                  S’(Set) input is active LOW, Latch will be Set(Q = 1)
                                  R’(Reset) input is active LOW, Latch will be Reset(Q = 0)

  • Active LOW input S’-R’ Latch implemented with two cross coupled NAND gates produces two complementary outputs , denoted as Q and Q’.
  • When Q is LOW , Q’ is HIGH. When Q is HIGH , Q’ is LOW.

                                         

Case 1 :

S’ = 0       R’ =1    
If either or both inputs are LOW , the output of the NAND gate will be HIGH. So ,
Q = 1       Q’ = 0
When the Q output is HIGH , the latch is in the SET state.

Case 2 :

S’ = 1        R’ = 1
S’ input changes to 1.Then Q output will stay at 1,maintaining the previous state. In this case, there is no change in the outputs. This is called MEMORY state.

Q = 1         Q' = 0

Case 3 :

S’ = 1    R’ = 0
If either or both inputs are LOW , the output of the NAND gate will be HIGH. So,
Q = 0   Q’ = 1
When the Q output is LOW , the latch is in the RESET state.


Case 4 :

S’ = 1      R’ = 1
Transitioning the R’ input to 1 without any change in the S’ input results in the Q output maintaining its previous state at 0, leading to a MEMORY state where the outputs remain constant.
Q = 0    Q’ = 1

Case 5 :

S’ = 0     R’ = 0
Q = 1      Q’ =1

This is forbidden for both Q and its complement Q’ to be in the state where both are 1 simultaneously. This condition is known as an indeterminate state because it violates the fundamental property that Q and Q’ should be complementary. And also this state can’t predict the next state.

As an example , in the next state, where  Set(S) equals 1 and  Reset(R) equals 1 , output will  depend on the propagation delay of the logic gates.  



Function Table of the Active LOW input S'-R' Latch












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