Gated D - Latch

Gated D - Latch

  • In a D latch, there's a single data input, labeled D, in addion to the enable input.
  • When the enable input is HIGH and the D input is HIGH, the Q output will be HIGH.
  • When the  enable input is HIGH and the D input is LOW, the Q output will be LOW.
  • In simpler terms, the input provide to the D input is reflected ath the Q output when the enable input is HIGH.
  • When the enable input is LOW, the Q output retains its state, maintaining it held before the enable input transitioned to a LOW state.


Function Table of Gated D Latch



Waveforms with Gated D Latch



If the above waveforms are applied to Gated D latch. Draw the resulting Q waveform assuming Q starts RESET(0). 
  • The Q resulting waveform  is as follows.





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